On behalf of one of our customer in Sweden, we are looking for a RF IC Design Engineer.
- Long-term contracts 6+months.
- Good rates, ongoing needs.
- Full relocation to Sweden.
- EU Nationals Only.
The job involves block verification within company´s digital ASIC and FPGA projects. The goal of the block verification is to verify that the functional requirements of product blocks are fulfilled before tape-out of the ASIC or release of the FPGA.
The work includes:
- Verification planning
- Verification specification
- Verification environment (creation/adaptation/maintenance).
- Test case creationUsage of uVC´sDevelopment of uVC´s (if needed)
- Usage of reference models (if needed)Constrained random testing
- Creation of Coverage matrix
- Writing Verification Reports
Most of the verification uses constrained random methodology but also dedicated test-vectors and assertions are used. A successful candidate is an experienced verification engineer with 5 or more years of IP module verification experience in System Verilog with the UVM methodology. Good understanding and knowledge about HW designs are also key factors. To have Specman, e knowledge and experience is a bonus. Good communication skills and interpersonal cooperation is required.
- Master degree or similar.
- Experienced in using the System Verilog tools and UVM methodology.
- Excellent programming skills (SV).
- Experience of SW design for an embedded environment.
- Knowledge of hardware design (VHDL/Verilog).
- Good knowledge of verification methodology in general.
- Experience in HW verification using e.g. OVM/UVM.
- Experience in system level verification.
- Experience in Formal Verification.
- Experienced in WCDMA, GSM and/or LTE systems.
- Good programming skills (C).
Start date: ASAP (depends on the availability).
End Date: 6+months contract, ongoing.
Location: Lund, Stockholm.